Conventional standard cell libraries in semiconductor integrated circuits (IC) primarily contain a logic cell layout based in a metal oxide semiconductor (MOS) environment, in particular a complimentary metal oxide semiconductor (CMOS) environment. A standard cell is a pre-designed layout of transistors or non-specific collection of logic gates that are typically designed with computer assisted design (CAD) applications. The cells are usually interconnected or wired together in a particular manner with means of a placement and routing tool to perform a specific type of logical operation in an application specific IC (ASIC). A conventional ASIC layout is typically defined by an array of logic cells arranged in adjacent rows. Such a row 10 is shown in FIG. 1. The row of cells is depicted for illustrative purposes as a layout representation of abutting logic cells 12,31,32,33,35 bound by power and ground rails 14,16. Each logic cell defines a specific logic circuit. The active areas or components of the logic cell include negative-channel diffusion 24, positive-channel diffusion 26, and gate 34 layers. The components of the logic cells are wired internally with vias 28 and metal layer 18,20,22 to form simple logic (NMOS and PMOS) gates to perform Boolean and logic functions, for example INVERTER (or NOT) 12,35, AND, OR, NAND 31, NOR 32, 33 XOR, XNOR, ADDERS, FLIP-FLOP, and the like. In the design of the interconnection layout, integrated circuit design rules must be observed, for example, minimum width of transistor width, minimum width of metal tracks, and the like.
Recent advances made in semiconductor technology have enabled cell library layout designers to work on the nanometer scale. However, as a result of this technology scaling, additional problems have surfaced concerning the physical properties of the ASIC. Such a problem includes stress occurring in materials near an interface of different materials with different crystallographic structures or thermal expansion coefficients. The stress creates strain in the active and shallow trench isolation (STI) regions 36 within the cell. The strain related with these physical interactions substantially effects the characteristics of the component transistors in the integrated circuit. For example, in the NMOS and PMOS devices, such as field effect transistors (FET), the impact of the stress may be severe and result in 10% or more variation of output performance. Noticeably, in the NMOS devices, lattice strain is responsible for a reduction in the current between source and drain (ID). A similar variation is reflected in the PMOS device, however, the fluctuation is a positive increase which actually is a beneficial variation improving the PMOS device performance.
Thus, there is a need for a method to avoid the reduction in drain current which is effected adversely by lattice stresses between the active regions and STI regions of the transistor devices of semiconductor integrated circuits.